EDA Week in Review

July 8-12, 2002

The EDA Consortium's Market Statistics Service released 1Q2002 industry revenues of $962 million, compared to $989 million in 1Q2001. The industry has generated over $900 million in revenue for eight consecutive reporting quarters. Revenue growth in EDA Products and Maintenance and Semiconductor Intellectual Property was not enough to overcome decreases of over 40 percent in Services revenue, leading to an overall revenue decline in Q1. Total revenue as reported by the MSS decreased three percent in 1Q2002,compared with 1Q2001.

High growth rates were seen in specific EDA application areas, such as IC/ASIC Design Planning & Floorplanning Tools (80 percent growth over 1Q2001), Analysis Tools for IC/ASICs (58 percent growth), and Other IC Layout Tools and Reticle Enhancement Technology (RET, 34 percent growth). This growth indicates the need to immediately accommodate rapidly shrinking silicon geometries, noted Wally Rhines, chairman of EDAC and chairman and CEO of Mentor Graphics Corp.

For the full results, see http://www.edac.org/MSSQ12002_FINAL.htm.

Synopsys, Inc. announced a full line of memory intellectual property (IP), which includes memory models, memory controllers, and memory BIST. The memory solution, as part of the DesignWare IP Library is available to designers through a single license and price, with no per-use fees or royalty payments.

The DesignWare IP Library provides a suite of memory IP designed to work together seamlessly in any design. The ability to use pre-designed, pre-verified IP blocks is key in enabling designers to dramatically reduce the time spent creating and verifying memory subsystems. The silicon-proven DesignWare memory solution ensures designers have access to the highest performance, easiest-to-integrate IP available.

The company said that the number of pre-verified memory simulation models in the DesignWare IP Library is constantly growing, with more than 10,000 models covering more than 25 memory vendors' devices available. The models integrate with simulators through the industry de facto standard SWIFT interface, which is supported by all Synopsys simulators and by all other major simulator vendors.

Magma Design Automation, Inc. launched a program to pre-qualify libraries for customer-owned tooling (COT) flows based on Magma's IC implementation system. With its FixedTiming methodology, gain-based synthesis and unified data model architecture, Magma's said its IC implementation system could leverage the pre-qualified libraries to deliver significantly improved performance. Magma said it has developed a comprehensive qualification process that includes generation and verification of parasitic, design, antenna and electromigration rules as well as routability analysis. Through this qualification process Magma believes that libraries are complete, include correct design rules and are ready for immediate use in the Magma flow. Dolphin Technology, Inc. is the first Magma partner to have a 0.13-micron library targeted to a leading foundry process.

HPL Technologies, Inc. signed a definitive agreement to acquire IDS Software Systems, Inc. (IDS), based in Silicon Valley, a privately held software development company. The acquisition is expected to close on or before the last day of this month. IDS' dataPOWER product is an interactive multi-platform yield and statistical analysis system for the semiconductor industry, specifically for IDMs, foundries and fabless companies. dataPOWER performs engineering analysis functions through an exploratory front-end for interactive access to manufacturing data. Under the terms of the agreement, HPL will acquire all outstanding shares of IDS for $23.0 million in cash and approximately 5.2 million shares of HPL common stock, and assume all IDS employee stock options, which will convert into approximately 300,000 HPL stock options. HPL said this acquisition would expand its market reach, through complementary applications with a strong installed base that includes companies such as Analog Devices, Intel, LSI Logic, Motorola, NEC, OKI, Philips, Texas Instruments (TI), and Toshiba.

Mentor Graphics Corp. introduced FPGA Advantage 5.3, the latest version of its HDL design flow for managing the creation, simulation and synthesis of FPGA devices. New features in the tool include design management features, such as enhanced Interface-Based Design (IBD) support and advanced debugging features, which simplify and ease the design of multi-million gate FPGAs. Mentor said the FPGA Advantage 5.3 IBD editor solves problems design engineers have with complex interconnect creation. IBD allows complex interconnect structures to be viewed in a compact tabular format. Users can rapidly specify the signal connections and automatically generate the equivalent structural description in VHDL or Verilog. The IBD tabular format also enables design constraints and synthesis properties to be specified and then be propagated to the downstream phases of the design flow. Also, FPGA Advantage's debugging capabilities have been expanded with version 5.3 to include visualization of text files during interactive simulation debug. These graphical and tabular diagrams of HDL source code enhance HDL simulation and improve design verification productivity.

Mentor Graphics also reported that Faraday Technology Corp. has selected its Design-for-Test (DFT) tools for its SoC design flows. Faraday said it selected Mentor Graphics for its proven DFT technology and ability to improve productivity and test quality and reduce test cost. Faraday also said it would use the FastScan tool for automatic test pattern generation and the MBISTArchitect tool for memory built-in self-test. Faraday also bought the BSDArchitect tool for automated boundary scan implementation, the DFTAdvisor tool for scan synthesis and testability analysis and the DFTInsight tool for graphical DFT debug and analysis.

Zenasis Technologies, Inc. closed its second round of funding with an investment from WestBridge Capital Partners. The additional second round investment by WestBridge Capital brings the total amount raised to $10 million since Zenasis was founded in 2000. Funds will be used as working capital to expand Zenasis' research and development efforts. Sigma Partners led its second round of funding in March 2002, followed by Selby Ventures and VentureTech Alliance.

MontaVista Software, Inc. and Xilinx, Inc. announced that MontaVista Linux Professional Edition would support the Xilinx Virtex-II Pro FPGA, which enables developers of embedded Linux products to target a completely programmable, re-programmable and field-upgradeable system platform. The collaboration allows the broad base of Linux developers to accelerate their embedded designs with the ability to reconfigure, enhance and optimize those designs throughout the entire product development life cycle. This announcement represents the first time FPGA-based systems developers can build and deploy on a Linux platform.

The integration of the Virtex-II Pro hardware platform with embedded Linux yields a flexible design environment, in which engineers can lower product costs and accelerate their time to market. Consequently, developers will benefit from the advantages of open source software to lower their product costs on a single, company-standard hardware platform that can target many different applications. This facilitates a quick start to design projects and supports fixes, enhancements and performance optimization to hardware or software throughout the entire product development process.

Xilinx has joined the MontaVista Partnering program, which gives users access to a world-class group of hardware and software providers who have embraced MontaVista Linux. With a wide variety of partners from which to choose, the program is dedicated to offering solutions to customer challenges. MontaVista has also joined Xilinx's Alliance program of industry partners, providing a full eco-system of support, including EDA, IP cores, design service, reference design and embedded solutions for the Virtex-II Pro.

@HDL announced that Toshiba Corp. has selected @HDL software for use on upcoming chip development projects. Toshiba said it selected the @Designer graphical debugging and design analysis product from @HDL after an extensive evaluation. Toshiba semiconductor engineers developing large-scale SoC designs will use the @Designer tool, the companies said.

Celestry Design Technologies, Inc. rolled out a universal model, AgeMOS, for accurate reliability modeling during deep-sub micron CMOS circuit simulation. Celestry is also announcing tools and services that support model development and reliability modeling options for its transistor-level circuit simulators. AgeMOS models enable the flexibility of incorporating new degradation mechanisms for transistor degradation analysis into a circuit simulation, and are more accurate than previous generations of reliability models. They work with popular transistor-level circuit simulators, like Celestry's UltraSim, a multi-million-transistor simulator.

Improv Systems announced the Crescendo Solution Kit that enables the development of low-power, multi-standard processor cores for broadcast and streaming media applications. Crescendo is a programmable core that can support multiple standards at low clock rates, making it ideally suited for the media processing market, the company said. The architecture of the Crescendo Solution Kit eliminates the need for multiple, single-purpose chips found in many portable and home consumer devices such as 3G phones, PDAs, set-top boxes, Personal Video Recorders, DVDs and TV on PCs. Tuned to the specific needs of the broadcast and mobile media domains, the Crescendo Solution Kits combine and integrate Improv's configurable DSP technology and methodology; a suite of application software; SOC integration and extension capabilities, including ARM/MIPS interfaces; a full SOC verification environment and tool suite; and a reference platform.

Leopard Logic, Inc. appointed Stefan Tamme to vice president of sales and marketing. Tamme will be responsible for directing and expanding Leopard Logic's business activities worldwide. Tamme has 14 years of high-tech experience, holding various engineering, marketing and sales management positions. He joins Leopard Logic from AXYS Design Automation, Inc. where he was vice president of marketing and sales, worldwide. In this role, he was instrumental in positioning the company as the premier source for verification solutions for multi-core SoC designs. Under his leadership, AXYS Design's worldwide customer base expanded to include industry leaders such as STMicroelectronics, Matsushita Electric (Panasonic), Infineon Technologies, ARC International, Adelante Technologies and others. Prior to joining AXYS Design, Tamme spent 8 years at sci-worx (Sican), now a subsidiary of Infineon Technologies. As president of sci-worx Corp. and vice president of international business development at sci-worx GmbH, Tamme was responsible for the international sales operations of the company and instrumental in establishing sci-worx as one of the leading semiconductor IP suppliers for communications and multimedia applications. Tamme's extensive experience includes technical marketing, management and design functions in the areas of software, system, ASIC and FPGA design, rapid prototyping and hardware emulation with companies like GateField (now Actel), Zycad and Bosch.

Synchronicity, Inc. announced the availability of IP Gear Fundamentals web-based training for IP Gear Publisher Suite, the company's solution for design reuse and the distribution and support of semiconductor intellectual property. The Publisher Suite is boosting the productivity of leading electronic product developers such as Philips, Toshiba, Hitachi, PMC Sierra, Mitsubishi, Conexant and Sharp, according to Synchronicity. The new course, built in conjunction with Vitalect, is aimed at end-users of IP Gear Publisher Suite, and will provide an effective means of educating engineers on design reuse. IP providers, such as ARM and inSilicon, have purchased the Publisher Suite to manage, distribute and/or support their IP and their customers could also use this training. Vitalect offers a hosted Learning Content Management System that includes course management, authoring, administration and tracking. Through Vitalect's web-based training program, Synchronicity customers around the globe now can access quality web-based training whenever they want. Web based training course on IP Gear, DesignSync, DesignSync DFII, and ProjectSync are available now through Synchronicity's website, http://www.synchronicity.com/Services/Training/wbt/wbt.html.

ViASIC, Inc. announced that Max Lloyd has been named president and chief executive officer of the company. Laura Zavelson, cofounder and former CEO, has been named CFO, and Bill Cox, cofounder, remains CTO. In addition, the company announced the receipt of Series 'A' funding from a corporate investor whose name was not disclosed. ViASIC was founded in 2000 to develop high-capacity routing software for designers and manufacturers of high-density, sub-130 nanometer ASICs and SoCs with up to 50 million gates. ViASIC's high capacity routing software, currently under development, will be a standalone “smart” routing tool that fills the gap between physical synthesis and manufacturing, the company said. Lloyd was previously vice president of business development at ASIC International (AI). While at AI, Lloyd built the sales and marketing infrastructure, oversaw product direction, and grew revenues by more than 500 percent in less than two years. He was a key member of the management team that prepared the company for acquisition and then sold the company to Flextronics in 2001. Before AI, he was head of East Coast sales for Avant! Corp., which was recently acquired by Synopsys, Inc. Lloyd received a degree in Mathematical Science and Computer Science from the University of North Carolina at Chapel Hill. He currently serves on the Board of Directors for Healthspex Corp., a laboratory diagnostics company.

Monterey Design Systems was issued two patents by the United States Patent and Trademark Office for its physical design technology, bringing its patent count to seven. Patent number US 6,367,051 is titled, “System and Method for Concurrent Buffer Insertion and Placement of Logic Gates” and patent number US 6,385,760 is titled, “System and Method for Concurrent Placement of Gates and Associated Wiring.” Both of these patents apply to the physical IC design technology that serves as the foundation for the Monterey Sonar physical prototyper and Dolphin physical implementation products, the company reported.

Nassda Corp. announced that Ramtron International Corp. has purchased Nassda's HSIM hierarchical full-chip simulator and analysis tool for use in the development of Ramtron's memory technologies under a license agreement. Under the terms of the agreement, Nassda will license HSIM to Ramtron for use in development flows for all Ramtron products including Enhanced SRAM and ferroelectric random access memory (FRAM). For this agreement, Nassda augmented HSIM with direct support for ferroelectric capacitor elements ­ the ferroelectric crystals that lie at the core of Ramtron's next-generation FRAM memory technology. Prior to this enhancement, HSIM users had to model ferroelectric capacitors with redundant subcircuits that did not provide optimal performance.

Verplex Systems, Inc. has won the Electron d'Or award (sponsored by the French electronics journal, Electronique) in France for EDA tool of 2002 for its high performance, market leading Conformal Logic Equivalence Checker (LEC). The Electron d'Or awards honor the best electronics products of the year as chosen by a jury of industry experts and end users. The panel cited Conformal's superior performance, capacity and ease-of-use as the reasons underpinning its success.

Elixent's D-Fabrix Reconfigurable Algorithm Processor (RAP) technology won the Design Award for Innovation at the EIDA Gala Awards Dinner in the U.K. The awards, voted for by readers of Electronics Weekly, New Electronics and Electronic Product Design, are a benchmark for how any new technology is thought of by the industry.

AccelChip, Inc. provider of high-level synthesis tools for DSP design, appointed Rick Carlson as vice president of worldwide sales. Carlson was most recently vice president of worldwide sales at Averant, Inc. Prior to AccelChip and Averant, Carlson was the vice president of worldwide sales at Synplicity from 1995 to 1999 where he established their successful U.S. and international sales channels. Carlson has also held executive and sales management positions with Escalade, Globetrotter, EDA Systems, Daisy Systems, Mentor Graphics and Calma. Carlson was a founder of the Electronic Design Automation Consortium (EDAC) and holds a B.S. Mathematics from the Illinois Institute of Technology.

Evatronix S.A. joined the Altera Consulting Alliance Program (ACAP). As a result, Altera Corp. customers in Eastern Europe will have access to Evatronix's design services for industrial automation, telecommunications and medical applications. Evatronix designs with a wide range of Altera devices, including Altera's recently introduced Stratix devices and Excalibur embedded processor solutions.

Altera Corp. and OSE Systems, Inc. announced the availability of the OSE real-time operating system (RTOS) for Altera's Excalibur embedded processor solutions. With this partnership, customers building communications and safety-critical systems can now design platforms for next-generation network infrastructures and mission-critical applications with 99.999 percent availability, (also known as high availability), the companies explained. Altera's Excalibur devices, with an ARM922T processor subsystem integrated with an FPGA architecture, and OSE's high-availability RTOS allow customers to take advantage of a close integration of high-performance custom logic for system-on-a-programmable-chip (SOPC) designs.

Atrenta Inc. and Xilinx, Inc. announced the release of new capabilities and Virtex-specific rules for Atrenta's SpyGlass software. Atrenta worked directly with Xilinx to define, develop and test a comprehensive set of rules that helps designers identify downstream issues early in the design cycle, the companies reported. This rule deck for SpyGlass performs structural analysis on Verilog and VHDL RTL code to help ensure that code meets advanced design requirements and FPGA design best practices. Unlike conventional RTL checkers that simply analyze the text and infer potential problems, SpyGlass employs predictive analysis technologies including fast-synthesis and logic evaluation to create a structural representation of the RTL in order to perform in-depth analysis early in the design cycle. This allows SpyGlass to be more precise in pinpointing problems while more accurately guiding the user to the best results.

Atrenta developed an extensive set of rules focused on helping the user quickly identify RTL constructs that should be changed to ensure compliance and best practices. SpyGlass also detects potential synthesizability and simulation problems in the RTL, thus avoiding time-consuming rework. The first release of this Xilinx predictive analysis solution is comprised of a set of rules that includes Virtex-specific rules and good FPGA design practices. SpyGlass also checks for other advanced design issues.

MoSys, Inc. announced that seven new companies have joined the MoSys 1T-SRAM Design Services Alliance (DSA) bringing the program to over 20 member companies. The DSA program provides 1T-SRAM licensees with specialized support as the 1T-SRAM technology is increasingly used in SoC designs. The seven new members are: Accent (Italy), Ardentec (Taiwan), Comit Systems (U.S.), Faraday (Taiwan and U.S.), Global UniChip (Taiwan), RealVision (Japan) and Sidsa (Spain). To read more news, click here.

--Ann Steffora, Managing Editor